Liquid crystal display (LCD) techniques have being developed rapidly in the last decade with a great advance from the screen size to the display quality. The performances of LCDs have reached those of conventional cathode ray tubes (CRTs) in all respects with the continuous efforts, thus LCDs take a leading role as a substitute for CRTs.
As the production of LCDs increases, the intense competitions among manufacturers enable the enhancement of the product performances, with a focus on improving of the image quality of LCDs. Flickering and Mura (a phenomenon of poor image quality) are two main defects among those that affect the image displaying quality of LCDs. As well known, a TFT LCD displays a complete and accurate image by controlling a voltage applied on each of the sub-pixels arranged in a matrix so as to adjust the brightness of each sub-pixel. Each sub-pixel uses a TFT as a switching element. When an ON voltage (Von) is applied to the gate electrode of a TFT in a certain row, the TFT is turned on, and a signal from data lines is applied to a pixel electrode of the sub-pixel. When an OFF voltage (Voff) is applied to the gate electrode of the TFT, the TFT is turned off. The voltage difference between the pixel electrode and a common electrode that are facing each other determines the orientation of the liquid crystal molecules within the sub-pixel region, and thereby determines the luminance and display quality of the sub-pixel. However, since the gate electrode and the source electrode are overlapped in the TFT, a parasitic capacitance Cgs is produced, which is represented by Cgs=ε0εnA/d, where ε0 represents the vacuum dielectric constant, εn represents the dielectric constant of a semiconductor material (e.g., n+ amorphous silicon (n+ a-Si)), A represents the overlapping area between the gate electrode and the source electrode, and d represents the vertical distance between the two metal layers of the gate electrode and the source electrode. As shown in FIG. 1, when the image display of the n-th frame begins, the level of gate signal on the x-th row jumps from Voff to Von, the TFT is turned on, data signal is applied, and the charging of the sub-pixel begins. The voltage Vp applied on the sub-pixel starts increasing and quickly approaches the level of data signal Vd. After the charging of the sub-pixel is completed, the gate signal level on the x-th row jumps back to Voff. The same operation repeats for the (x+1)-th row. When the gate voltage applied on the x-th row is changed back to Voff from Von, a voltage difference ΔVp is produced on the sub-pixel due to the overlapping of the gate electrode and the source electrode. That is, when the gate voltage is changed back to Voff from Von and thereby the TFT is turned off, Cgs may result in the voltage difference ΔVp on the sub-pixel. If Cgs is reduced, ΔVp can also be effectively decreased (from ΔVp to ΔVp′, and ΔVp>ΔVp′), according to the equation of ΔVp=[Cgs/(CLC+Cgs+Cst)]ΔVg, where CLC represents the capacitance of the LC layer, Cst represents a storage capacitance, ΔVp represents a voltage change produced on the sub-pixel when the gate voltage is changed from Von to Voff, and ΔVg is the difference between the Von and Voff.
FIGS. 2a, 2b and 2c are top plan views of three kinds of sub-pixels of the TFT LCDs in the related art. FIG. 2a shows a sub-pixel structure in which a storage capacitor Cst is formed by a gate line 1. The sub-pixel includes the gate line 1 (gate metal layer), an active layer 3, a data line (source/drain electrode metal layer) 4, a pixel electrode 6, a drain electrode 7, and a source electrode 8, wherein the storage capacitor Cst is formed in an overlapping area 10 between the pixel electrode 6 and the gate line 1. The gate line 1 and the data line 4 cross with each other and define a pixel area. The pixel electrode 6 is connected with the source electrode 8 via a via hole 15 (also see FIG. 3b). The sub-pixel structure of FIG. 2b is similar to that of FIG. 2a, except addition of two light blocking bars 11 in the gate metal layer The sub-pixel structure of FIG. 2c includes light blocking bars the same as those in FIG. 2b, and the storage capacitor Cst is formed by a storage common electrode comprising the storage common electrode 12 in the gate metal layer. The storage capacitor Cst is formed in an overlapping area 13 between the pixel electrode 6 and the storage common electrode 12 in the gate metal layer. FIG. 3a shows a schematic view of each sub-pixel comprising the gate metal layer 1, a gate insulation layer 2, the active layer 3, the source/drain electrode layer 4, a passivation layer 5, and the pixel electrode 6 stacked sequentially from bottom to top. The above three kinds of sub-pixels have the same TFT structure. FIG. 3b shows a cross-sectional view of the sub-pixel shown in FIG. 2a taken along the line 3b-3b of FIG. 2a, and the stacked layers are also shown in FIG. 3b. 
A channel structure of the TFT in the related art is shown in the enlarged view of FIG. 4a. The profile of the channel between the source electrode and drain electrode in the active layer 3 is a straight line, and the channel region formed between the source electrode 8 and drain electrode 7 has no undulation as a whole (i.e., the edges of channel in the width direction have no undulation when the channel length is constant). FIG. 4b shows a cross-sectional view taken along the line 4b-4b of FIG. 4a. A parasitic capacitor Cgs is produced in an overlapping area 9 between the gate electrode 1 and the source electrode 8, which is inevitable in TFT device design. The Cgs may affect the value of the voltage change ΔVp on a sub-pixel, causing the flickering. Furthermore, in the manufacture process, the actual values of a width/length ratio (W/L) of the channel in TFTs vary between different display areas due to the factors such as instability of process and apparatus, resulting in different degrees of charging for sub-pixels in different areas. For example, when it is desired to display a certain gray level in the whole display screen, mura occurs in which some areas have an excessive luminance (whitening) while other areas have an inadequate luminance (darkening), due to different ΔVp of sub-pixels in different areas caused by different degrees of charging for sub-pixels in different areas.